1. Technical Field
This disclosure relates to integrated circuit (IC) design, and more particularly to testing of integrated circuit logic designs.
2. Description of the Related Art
During the IC design cycle, the design must be validated or verified to ensure that the design functions the way that it was intended to function. One way to verify the design is to perform some level of verification. Accordingly, verification includes providing some stimulus to the IC design, monitoring the results during simulation, and determining whether the stimulus exercised the IC design adequately to determine whether or not the design does function as it was designed to. Accordingly, the concept of coverage arises. Coverage refers to the concept of a verification engineer or other designer judging the stimulus applied to a system to verify the IC design.
There are several kinds of coverage available, some of which may be easy to automate. For example, line, path, toggle, and finite state machine coverage may be easily automated. In addition, exhaustive coverage which may test every possible state may be possible on small designs. However, as designs have increased in size and complexity, the number of possible states to cover can approach infinity. Thus, another coverage type may be more appropriate. Functional coverage is a more sophisticated type of coverage that usually involves having knowledge of the architecture of the design so that a relationship between signals can be defined and used to develop the desired coverage. Thus, of the nearly infinite number of states, the states that are the most interesting are selected. However, one drawback of obtaining adequate functional coverage is that the selection process can be both time and resource intensive.
In addition, even if a given internal state failure can be detected during simulation, these internal states may not be architecturally visible during testing of the manufactured device. Thus, identifying test vectors that can propagate and detect these internal failures at the architectural level can be difficult and time consuming.